Probability-based approaches to VLSI circuit partitioning

نویسندگان

  • Shantanu Dutt
  • Wenyong Deng
چکیده

Iterative-improvement 2-way min-cut partitioning is an important phase in most circuit placement tools, and finds use in many other CAD applications. Most iterative improvement techniques for circuit netlists like the FiducciaMattheyses (FM) method compute the gains of nodes using local netlist information that is only concerned with the immediate improvement in the cutset. This can lead to misleading gain information. Krishnamurthy suggested a lookahead (LA) gain calculation method to ameliorate this situation; however, as we show, it leaves room for improvement. We present here a probabilistic gain computation approach called PROP (PRObabilistic Partitioner) that is capable of capturing the future implications of moving a node at the current time. We also propose an extended algorithm SHRINK-PROP that increases the probability of removing recently “perturbed” nets (nets whose nodes have been moved for the first time) from the cutset. This is necessary, since in a regular move process, the removal probabilities of most nets either remain unchanged or even decrease when their nodes are moved for the first time. Experimental results on mediumto large-size ACM/SIGDA benchmark circuits show that PROP and SHRINK-PROP outperform previous iterative-improvement methods like FM (by about 30% and 37%, respectively) and LA (by about 27% and 34%, respectively). Both PROP and SHRINK-PROP also obtain much better cutsizes than many recent state-of-the-art partitioners like EIG1, WINDOW, MELO, PARABOLI, GFM and GMetis (by 4.5% to 67%). We also show that the space and time complexities of PROP and SHRINK-PROP are very reasonable. Our empirical timing results reveal that PROP is appreciably faster than all recent techniques except GMetis—all other partitioners including ours work on flat netlists, while GMetis uses multilevel clustering, which is a paradigm orthogonal to basic partitioning, and can be used in conjunction with any partitioner. Further, PROP is only a little slower than FM and LA, both of which are very fast (but give sub-optimal results). SHRINK-PROP is about two times slower than PROP, but still faster than most recent partitioners. We also obtain results on the more recent ISPD-98 benchmark suite that show similar substantial mincut improvements by PROP and SHRINK-PROP over FM (24% and 31%, respectively). It is also noteworthy that SHRINK-PROP’s results are within 2.5% of those obtained by hMetis, one of the best multilevel partitioners. However, the multilevel paradigm, as mentioned above, is orthogonal to SHRINK-PROP. Further, since it is a “flat” partitioner, it has advantages over hMetis in partition-driven placement applications.

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عنوان ژورنال:
  • IEEE Trans. on CAD of Integrated Circuits and Systems

دوره 19  شماره 

صفحات  -

تاریخ انتشار 2000